The present invention relates to direct digital synthesis (DDS) and particularly to a power and/or speed efficient pulse output DDS circuit. Specifically, the device is used to generate one or more clock signals for digital circuitry whereas the generated clock signals can have frequencies less than but arbitrarily relative to the frequency of the reference clock signal.
In many applications, it is necessary to generate multiple clock signals for clocking of digital circuits that process different streams of data at distinctly and/or subtly different rates. In those applications in which a suitable clock signal is not provided with each data stream, a local clock signal often needs to be generated and recovered from the data stream. An exemplary system that demonstrates this need is a multi-port receiver such as in a T3/E3/STS-1 line card. Each of the multiple ports must be capable of receiving and recovering data arriving at slightly different rates relative to the other ports; the rates are plesiochronous. Furthermore, it is possible that some of the ports are receiving STS-1 rate (51.84 MHz) data while other ports are receiving T3 rate (44.736 MHz) data. Clock signals are not supplied with the data signals, so clock signals must be generated locally within the receiver to process each data stream.
A classic system 10 for generating a suitable clock signal is depicted in FIG. 1a. An oscillating circuit 101 (e.g a ring oscillator or a crystal oscillator) designed to function at an approximate desired frequency is used to clock digital circuit 103. Through various means, digital circuit 103 (or optionally accompanying analog circuitry) adjusts the frequency of operation of the oscillating circuit such that the oscillating frequency matches the frequency of the received signal and is phase aligned appropriately to support digital processing.
For multi-port systems, a system 11 as illustrated in FIG. 1b may be used for generating multiple required clock signals by simply replicating system 10 for a single clock signal generator. A drawback to system 11 is that multiple independent oscillating circuits are required. For a highly integrated multi-port device, system 11 is relatively expensive and commercially uncompetitive.
Reference is now made to FIG. 2 which illustrates a prior art system 12, for generating multiple clock signals. In order to decrease cost and provide a competitive advantage, a pulse output Direct Digital Synthesis (DDS) clock generating or pulse output circuit 105 can be used. A “classic” DDS circuit typically outputs a sine wave. Pulse output DDS 105 is a simplified version of the classic DDS and generates a square wave signal (i.e., a clock) at the desired frequency. In system 12, multiple pulse output DDS circuits 105 are required, but only one reference oscillator 101 is required, as each pulse output DDS circuit 105 can use the same reference clock.
Reference is now made to FIG. 3, illustrating the structure of a classic DDS circuit 104 generating a sine-wave. DDS circuit 104 assumes that the output sine wave has a substantially lower frequency than the reference clock. An n-bit modulus −2π counter (adder 201 with feedback) and phase register 203 are implemented in circuit 104 as a phase accumulator 205 connected to a phase/amplitude lookup table or converter 207. A digital control word M of n bits is loaded into phase register 203. Phase accumulator is actually a modulus 2π counter that increments its stored number by digital word M each time it receives a clock pulse. The sine wave oscillation is visualized as a vector rotating around a phase circle. Each point on the phase circle corresponds to an equivalent point in the cycle of the sine waveform. As the vector rotates around the circle, a corresponding output sine wave is being generated. One revolution of the vector around the phase circle at a constant speed, results in one complete cycle 2π of the output sine wave. The number of available discrete phase points contained in the circle is determined by the resolution, or number of bits n, of phase accumulator 205. Phase accumulator 205 is utilized to provide the equivalent of the vector's rotation around the phase circle by increments of M. The contents of phase accumulator 205 correspond to the points on the cycle of the output sine wave. The output of phase accumulator 205 is linear and cannot directly be used to generate a sine wave or any other waveform except a ramp. Therefore, phase-to-amplitude (e.g. cosine) lookup table 207 is used to convert a truncated version (e.g. p most significant bits) of instantaneous output value of phase accumulator 205 into the sine wave amplitude information that is presented to the digital to analog (D/A) converter (not shown). The output of the digital to analog converter is filtered to produce the desired frequency sine wave (or cosine wave).
For use in digital circuit clocking, square waves are typically preferred over sine-waves, especially if clock jitter is an issue. Reference is now made to FIG. 4 which illustrates a prior art circuit 105 for generation of a clock signal. Circuit 105 is often called a pulse output DDS. The generic structure of a DDS circuit 104 is easily modified to produce a clock output. Instead of mapping the “p” most significant bits of phase accumulator 205 to a cosine table, a much simpler mapping can be used. When phase accumulator 205 represents a phase in the interval [0, π), the clock output is set to “1”. When phase accumulator 205 represents a phase in the interval [π, 2π), the clock output is set to “0”.
DDS circuits 104, 105 (for sine wave or pulse output) can be operated in open loop (i.e. free-run) or closed loop mode. In open loop mode, the ability to generate precise frequencies is affected by the resolution (number of bits n) of accumulator 205 and the frequency control word M. Depending on the relationship between the reference frequency fref and the desired output frequency, it may be possible to generate the exact required frequency with only a few bits of accumulator resolution; however, this is not the general case. Usually, it is not possible to generate the exact desired frequency with a finite resolution of the frequency control word M and accumulator 205. However, increasing the resolution N of accumulator 205 will decrease the achievable frequency error. In closed-loop mode, an external circuit or entity determines whether an increase or decrease in output frequency is needed and the frequency control word M is adjusted accordingly. As a result, the frequency control word is effectively dithered about some nominal value and any desired output frequency can be generated exactly. In this case, the resolution of accumulator 205 will impact the purity of the generated clock. With a lower resolution (smaller N) accumulator, more dithering of the accumulator control word M will generally be required resulting in an increased output clock jitter. With a higher resolution accumulator, less dithering of the accumulator control word M will be necessary and the resulting output clock will have less jitter. Dithering of the frequency control word about some nominal desired value is not restricted to closed loop operation. It is also possible to generate and apply a pre-determined dithering pattern to the frequency control word to improve the long-term average frequency of the generated clock.
In circuit 105, accumulator 205 is clocked at the reference clock rate, which can be significantly higher than frequency fgen of the desired output clock signal. As the number of multiple independent clocks to be generated increases, and/or the required reference clock frequency fref increases, and/or the required resolution of accumulator 205 increases, operating accumulator 205 at the reference clock frequency becomes challenging from either a size/power competitive viewpoint, or from the viewpoint of being able to synthesize a working circuit in the desired digital gate technology.
There is thus a need for, and it would be highly advantageous to have a pulse output DDS circuit that has superior operating characteristics relative to prior art pulse output DDS circuit 105 and particularly for practical digital devices in which multiple non-related clocks are required, such as a multi-port T3/E3 receiver in which each port is plesiochronous with each other.
Current state of the art of DDS circuits for clock generation is represented by the following publications, incorporated herein by reference for all purposes as if entirely set forth herein:                U.S. Pat. No. 5,673,212, Sep. 30, 1997, Robert Karl Hansen, “Method and Apparatus for Numerically Controlled Oscillator with Partitioned Phase Accumulator”        U.S. Pat. No. 6,064,241, May 16, 2000, Bainton et al., “Direct Digital Frequency Synthesizer using Pulse Gap Shifting Technique”        U.S. Pat. No. 6,642,754, Nov. 4, 2003, Dobramysl et al., “Clock Signal Generator Employing a DDS Circuit”        US Patent Application 20030058004, Mar. 27, 2003, Stengel et al. “Method and Apparatus for Direct Digital Synthesis of Frequency Signals” . . . same disclosure also filed as PCT WO03/027847, Apr. 3, 2003        
U.S. Pat. No. 5,673,212 describes a sinewave generating DDS circuit. The disclosure recognizes that the accumulator can be partitioned into two parallel accumulators: one for the Most Significant Bits (MSBs), and one for the Least Significant Bits (LSBs). Moreover, the accumulator for the LSBs can be clocked at a slower speed than the accumulator for the MSBs. The CO (Carry Out) bit of the LSB accumulator is applied to the CI (Carry In) of the MSB accumulator. As a result, the MSB accumulator that is operating at the reference clock frequency has a reduced bit width, simplifying the implementation for use with higher speed reference clocks.
U.S. Pat. No. 6,064,241 is a DDS based clock generator that addresses the issue of clocking the accumulator circuit by the high speed reference clock. The approach taken provides for the n-bit signed adder of the phase accumulator circuit to operate at a rate that is an integer sub-multiple of the reference clock, not at a rate equal to the reference clock frequency as with classic DDS circuits. The purpose of the phase accumulator circuit is to occasionally alter the operation of the Phase Shifter. Normally, the Phase Shifter outputs “I” output clock pulses for every “I+1” pulses of the high speed reference clock. The operation of the Phase Accumulator is to periodically adjust the value of “I” by +1 or −1. The output clock from the Phase Shifter is further divided by 6 to provide the final generated output clock. For applications in which the desired output clock has a frequency that is close to frefI/((6·(I+1)), where fref is the frequency of the high speed reference clock, and where I is a positive integer, the described disclosure may be useful.
U.S. Pat. No. 6,642,754 is another DDS based clock generator that addresses the issue of clocking the accumulator circuit by the high-speed reference clock. The approach taken is to have a cascade of two DDS circuits. A coarse DDS circuit is run at a sub-multiple of the reference clock frequency. The accumulator overflow of the coarse DDS indicates approximately when a clock output pulse should be generated. The output clock jitter of this DDS is typically too large, so a cascaded fine DDS circuit is used to improve the timing of the generated clock pulses. The fine DDS is operated at the reference clock frequency, but since it only operates when the coarse DDS overflows, the current consumption of the whole circuit is kept at a level only slightly higher than that of the coarse DDS portion. In this disclosure, the precision of the circuit operation is determined by the fine DDS circuit which is clocked at the high-speed reference clock frequency.
US Patent Application 2003/0058004 is yet another DDS based clock generator that addresses the classic DDS issue of clocking the accumulator circuit by the high-speed reference clock. This disclosure represents the ratio of the reference clock frequency to the generated output clock frequency as fref/fgen=Ninteger+Rfractional. Furthermore, a counter is operated at the reference clock rate, and when the count exceeds Ninteger, it triggers a fractional accumulator that accumulates the value Rfractional. The trigger output from the counter also triggers the generation of a clock pulse, with refinement of the temporal location of the pulse using information provided by the accumulation of Rfractional. Whenever a clock pulse is generated, the counter is reset. When the accumulator exceeds a value of Rfractional=1, it is reset to a value of: Rfractional−1. Therefore, the disclosure effectively partitions the circuit into a high speed portion counting the pulses of the reference clock, and a slow speed portion that only operates when the counter exceeds a defined threshold.